Datasheet

Section 10 I/O Ports
Page 664 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• PF2/LCAS*
7
/DQML*
6
/IRQ15-A/SSI0-C (H8S/2426 Group and H8S/2426R Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR*
7
of the bus controller, bits ABW5
to ABW2 in ABWCR, bits SSI0S1 and SSI0S0 in PFCR5, and bit PF2DDR.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
Areas 2 to 5 Any DRAM/
synchronous DRAM
space area is 16-bit
bus space
All DRAM/synchronous DRAM space areas are
8-bit bus space, or areas 2 to 5 are all normal space
SSU settings ⎯ (1) in table below (2) in table
below
(3) in table
below
PF2DDR ⎯ 0 1 0*
4
⎯
LCAS*
7
output
DQML*
6
output
PF2 input PF2 output SSI0-C
input*
2
*
5
SSI0-C
output*
3
*
5
Pin function
IRQ15-A interrupt input*
1
• Modes 3 and 7 (EXPE = 0)
Areas 2 to 5 ⎯
SSU settings (1) in table below (2) in table below (3) in table below
PF2DDR 0 1 0*
4
⎯
PF2 input PF2 output SSI0-C input*
2
*
5
SSI0-C output*
3
*
5
Pin function
IRQ15-A interrupt input*
1
Notes: 1. IRQ15 input when the ITS15 bit in ITSR is 0.
2. When using as SSI0-C input, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other
register setting.
3. When using as SSI0-C output, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other
register setting.
4. PF2DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSI0S1 and SSI0S0 = B'10 in PFCR5.
Use as I/O port.
6. Not supported in the H8S/2426 Group.
7. Not supported in the 5-V version.