Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 659 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name
Initial
Value R/W Description
7 PF7DDR 1/0
*
W
6 PF6DDR 0 W
5 PF5DDR 0 W
4 PF4DDR 0 W
3 PF3DDR 0 W
2 PF2DDR 0 W
1 PF1DDR 0 W
0 PF0DDR 0 W
• Modes 3 and 7 (EXPE = 0)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an input port
when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions can be
switched with PFDDR.
Notes: 1. PF7DDR is initialized to 1 in modes 1, 2, and 4, and to 0 in modes 3 and 7.
2. Not supported in the 5-V version.