Datasheet

Section 10 I/O Ports
Page 640 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• PC5/A5/TIOCB10
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOB3 to
IOB0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC5DDR.
Operating
mode
1, 2 4 3, 7 (EXPE = 1) 3, 7 (EXPE = 0)
TPU channel
10 settings
⎯ ⎯ (1) in table
below
(2) in table below
PC5DDR ⎯ 0 1 ⎯ 0 1
PC5 input PC5 output Pin function A5 output PC5 input A5 output TIOCB10
output
TIOCB10 input*
TPU channel 10
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'10
B'10
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯
[Legend]
x: Don't care
Note: * TIOCB10 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.