Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 611 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
10.9.2 Port A Data Register (PADR)
PADR stores output data for the port A pins.
Bit Bit Name Initial Value R/W Description
7 PA7DR 0 R/W
6 PA6DR 0 R/W
5 PA5DR 0 R/W
4 PA4DR 0 R/W
3 PA3DR 0 R/W
2 PA2DR 0 R/W
1 PA1DR 0 R/W
0 PA0DR 0 R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
10.9.3 Port A Register (PORTA)
PORTA shows the pin states of port A. PORTA cannot be modified.
Bit Bit Name Initial Value R/W Description
7 PA7 ⎯* R
6 PA6 ⎯* R
5 PA5 ⎯* R
4 PA4 ⎯* R
3 PA3 ⎯* R
2 PA2 ⎯* R
1 PA1 ⎯* R
0 PA0 ⎯* R
If this register is read while a PADDR bit is set to 1,
the corresponding PADR value is read. If this
register is read while a PADDR bit is cleared to 0,
the corresponding pin state is read.
Note: * Determined by the states of pins PA7 to PA0.