Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 609 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
10.9.1 Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit Bit Name
Initial
Value R/W Description
7 PA7DDR 0 W
6 PA6DDR 0 W
5 PA5DDR 0 W
4 PA4DDR 0 W
3 PA3DDR 0 W
2 PA2DDR 0 W
1 PA1DDR 0 W
0 PA0DDR 0 W
• Modes 1 and 2
Pins PA4 to PA0 are address outputs.
For pins PA6 and PA5, when the corresponding bit of A22E
and A21E is set to 1, setting a PADDR bit to 1 makes the
corresponding pin an address output, while clearing the bit to
0 makes the corresponding pin an input port. Clearing one of
bits A22E and A21E to 0 makes the corresponding pin an I/O
port, and its function can be switched with PADDR.
When A23E is 1, the PA7 pin functions as an address output
pin when the PA7DDR bit is set to 1, and as an input port
when the bit is cleared to 0.
When A23E is 0, operations differ between the H8S/2426
and H8S/2426R Groups and H8S/2424 Group.
[H8S/2426 Group and H8S/2426R Group]
When the PA7 pin is a general I/O port, the function can be
switched with PA7DDR.
[H8S/2424 Group]
When the CS output enable bit (CS7E) is 1, the PA7 pin
functions as a CS7 output pin when the PA7DDR bit is set to
1, and as an input port when the bit is cleared to 0. When the
CS output enable bit (CS7E) is 0 and the PA7 pin is a
general I/O port, the function can be switched with PA7DDR.