Datasheet

Section 10 I/O Ports
Page 604 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bit TE in SCR_3 of the SCI,
bits PPGS, TPUS, and TMRS in PFCR3, and bit P81DDR.
TPU channel 3
settings
(1) in table
below
(2) in table below
TE 0 1
P81DDR ⎯ 0 1 ⎯
NDER1 ⎯ ⎯ 0 1 ⎯
P81 input P81 output PO1-B output*
3
TxD3 output TIOCB3-B
output*
4
TIOCB3-B input*
1
*
4
Pin function
TMRI1-B input*
2
*
5
Notes: 1. TIOCB3-B input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx
2. When used as the counter reset input pin for the TMR, the external reset should be
selected using the CCLR1 and CCLR0 bits in TCR_1 and TMRIS bit in TCCR_1 after
the TMRS bit in PFCR3 is set to 1.
3. When using as PO1-B output, set PPGS in PFCR3 to 1 before other register setting.
4. When using as TIOCB3-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
5. When using as TMRI1-B input, set TMRS in PFCR3 to 1 before other register setting.
TPU channel 3
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'010
B'010
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯