Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 597 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P84/IRQ4-B/EDACK2
The pin function is switched as shown below according to the combination of bit AMS in
EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR of the interrupt controller.
Operating mode 1, 2, 4 3, 7 (EXPE = 1) 3, 7 (EXPE = 0)
AMS 0 1 ⎯
P84DDR 0 1 ⎯ 0 1
P84 input P84 output EDACK2 output P84 input P84 output Pin function
IRQ4-B interrupt input*
Note: * IRQ4-B input when the ITS4 bit in ITSR is 1.
• P83/ETEND3/IRQ3-B/RxD3/PO3-B/TIOCD3-B/TMCI1-B
The pin function is switched as shown below according to the combination of bit ETENDE in
EDMDR_3 of the EXDMAC, bit RE in SCR_3 of the SCI, TPU channel 3 settings (by bits
MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in
TCR_3), bit NDER3 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit
P83DDR, and bit ITS3 in ITSR of the interrupt controller.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
TPU channel 3
settings
(1) in table
below
(2) in table below
ETENDE ⎯ 0 1
RE ⎯ 0 1 ⎯
P83DDR ⎯ 0 1 1 ⎯ ⎯
NDER3 ⎯ ⎯ 0 1 ⎯ ⎯
P83 input P83 output PO3-B
output*
4
RxD3 input ETEND3
output
TIOCD3-B
output*
5
TIOCD3-B input*
2
*
5
IRQ3-B interrupt input*
1
Pin function
TMCI1-B input*
3
*
6