Datasheet

Section 10 I/O Ports
Page 590 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P62/IRQ10-A/TEND0/TMCI0-A
The pin function is switched as shown below according to the combination of bit TEE0 in
DMATCR of the DMAC, bit TMRS in PFCR3, bit P62DDR, and bit ITS10 in ITSR of the
interrupt controller.
TEE0 0 1
P62DDR 0 1 ⎯
P62 input P62 output TEND0 output
IRQ10-A interrupt input*
1
Pin function
TMCI0-A input*
2
*
3
Notes: 1. IRQ10-A input when the ITS10 bit in ITSR is 0.
2. When used as the external clock input pin for the TMR, its pin function should be
specified to the external clock input by the CKS2 to CKS0 bits in TCR_0.
3. When using as TMCI0-A input, set TMRS in PFCR3 to 0 before other register setting.
• P61/IRQ9-A/DREQ1/TMRI1-A
The pin function is switched as shown below according to the combination of bit TMRS in
PFCR3, bit P61DDR, and bit ITS9 in ITSR of the interrupt controller.
P61DDR 0 1
P61 input P61 output
TMRI1-A input*
1
*
3
DREQ1 input
Pin function
IRQ9-A interrupt input*
2
Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits
in TCR_1 should be set to 1.
2. IRQ9-A input when the ITS9 bit in ITSR is 0.
3. When using as TMRI1-A input, set TMRS in PFCR3 to 0 before other register setting.