Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 583 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• Modes 3 and 7 (EXPE = 0)
BRLE
BREQS
⎯
ICE 0 1
TPU channel 3
settings
(1) in table
below
(2) in table below ⎯
RE ⎯ 0 1 ⎯
P51DDR ⎯ 0 1 1 ⎯ ⎯
NDER2 ⎯ ⎯ 0 1 ⎯ ⎯
P51 input P51 output PO2-B output*
6
RxD2 input SCL3 I/O*
5
TIOCC3-B
output*
7
TIOCC3-B input*
1
*
7
IRQ1-A interrupt input*
2
Pin function
TMCI0-B input*
3
*
8
TPU channel 3
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'101
B'101
Output function ⎯ Output compare
output
⎯ PWM*
4
mode
1 output
PWM mode
2 output
⎯
Notes: 1. TIOCC3-B input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. IRQ1-A input when the ITS1 bit in ITSR is 0.
3. When used as the external clock input pin for the TMR, its pin function should be
specified to the external clock input by the CKS2 to CKS0 bits in TCR_0 after the TMRS
bit in PFCR3 is set to 1.
4. TIOCD3-B output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_3.
5. NMOS open-drain output regardless of P51ODR.
6. When using as PO2-B output, set PPGS in PFCR3 to 1 before other register setting.
7. When using as TIOCC3-B input/output, set TPUS in PFCR3 to 1 before other register
setting.
8. When using as TMCI0-B input, set TMRS in PFCR3 to 1 before other register setting.