Datasheet

Section 10 I/O Ports
Page 582 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P51/RxD2/IRQ1-A/SCL3/BREQ-B/PO2-B/TIOCC3-B/TMCI0-B
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I 2 C, bits
MD3 to MD0 in TMDR_3 of TPU, bits IOC3 to IOC0 in TIORL_3, TPU channel 3 settings by
bits CCLR2 to CCLR0 in TCR_3, bit NDER2 in NDERL of PPG, bit RE in SCR_2 of the SCI,
bit P51DDR, bits PPGS, TPUS, and TMRS in PFCR3, and bit BREQS in PFCR4, and bit ITS1
in ITSR of the interrupt controller.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
BRLE
BREQS
BRLE = 0, or BRLE = 1 and BREQS = 0 BRLE = 1
and
BREQS = 1
ICE 0 1 ⎯
TPU channel 3
settings
(1) in table
below
(2) in table below ⎯ ⎯
RE ⎯ 0 1 ⎯ ⎯
P51DDR ⎯ 0 1 1 ⎯ ⎯ ⎯
NDER2 ⎯ ⎯ 0 1 ⎯ ⎯ ⎯
P51 input P51 output PO2-B
output*
6
RxD2 input SCL3*
5
I/O
BREQ-B
input
TIOCC3-B
output*
7
TIOCC3-B input*
1
*
7
IRQ1-A interrupt input*
2
Pin function
TMCI0-B input*
3
*
8