Datasheet

Section 10 I/O Ports
Page 566 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P22/PO2-A/TIOCC3-A/TMCI0-A
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2
to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in
PFCR3, and bit P22DDR.
TPU channel 3
settings
(1) in table
below
(2) in table below
P22DDR ⎯ 0 1
NDER2 ⎯ ⎯ 0 1
P22 input P22 output PO2-A output*
4
TIOCC3-A output*
5
TIOCC3-A input*
1
*
5
Pin function
TMCI0-A input*
2
*
6
TPU channel 3
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'101
B'101
Output function ⎯ Output compare
output
⎯ PWM*
3
mode
1 output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCC3-A input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. When used as the external clock input pin for the TMR, its pin function should be
specified to the external clock input by the CKS2 to CKS0 bits in TCR_0 after the TMRS
bit in PFCR3 is set to 0.
3. TIOCD3 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_3.
4. When using as PO2-A output, set PPGS in PFCR3 to 0 before other register setting.
5. When using as TIOCC3-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
6. When using as TMCI0-A input, set TMRS in PFCR3 to 0 before other register setting.