Datasheet

Section 10 I/O Ports
Page 564 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits
CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI,
bits PPGS, TPUS, and TMRS in PFCR3, bit TXD4S in PFCR4, and bit P23DDR.
TPU channel 3
settings
(1) in table
below
(2) in table below
TE ⎯ 0 1
P23DDR ⎯ 0 1 ⎯
NDER3 ⎯ ⎯ 0 1 ⎯
P23 input P23 output PO3-A output*
3
TxD4-A
output*
6
TIOCD3-A
output*
4
TIOCD3-A input*
1
*
4
Pin function
TMCI1-A input*
2
*
5
Notes: 1. TIOCD3-A input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
2. When used as the external clock input pin for the TMR, its pin function should be
specified to the external clock input by the CKS2 to CKS0 bits in TCR_1 after the TMRS
bit in PFCR3 is set to 0.
3. When using as PO3-A output, set PPGS in PFCR3 to 0 before other register setting.
4. When using as TIOCD3-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
5. When using as TMCI1-A input, set TMRS in PFCR3 to 0 before other register setting.
6. When using as TxD4-A output, set TXD4S in PFCR4 to 0 before other register setting.