Datasheet

Section 10 I/O Ports
Page 560 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P26/PO6/TIOCA5/SDA2/ADTRG1
The pin function is switched as shown below according to the combination of the TPU channel
5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1
and CCLR0 in TCR_5), bit NDER6 in NDERL of the PPG, bits TRGS1, TRGS0, and
EXTRGS in ADCR_1 of the ADC, bit ICE in ICCRA_2 of the I
2
C, and bit P26DDR.
ICE 0 1
TPU channel 5
settings
(1) in table
below
(2) in table below ⎯
P26DDR ⎯ 0 1 1 ⎯
NDER6 ⎯ ⎯ 0 1 ⎯
P26 input P26 output PO6 output SDA2 I/O*
4
TIOCA5
output
TIOCA5 input*
1
Pin function
ADTRG1 input*
3
TPU channel 5
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'01
B'01
Output function ⎯ Output
compare
output
⎯ PWM*
2
mode
1 output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. TIOCB5 output disabled.
3. ADTRG1 input when EXTRGS = 0 and TRGS1 = TRGS0 = 1.
4. NMOS open-drain output regardless of P26ODR.