Datasheet

Section 10 I/O Ports
Page 556 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P22/IRQ10-B /PO2-A/TIOCC3-A
The pin function is switched as shown below according to the combination of the TPU channel
3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2
to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit
P22DDR, and bit ITS10 in ITSR of the interrupt controller.
TPU channel 3
settings
(1) in table
below
(2) in table below
P22DDR ⎯ 0 1
NDER2 ⎯ ⎯ 0 1
P22 input P22 output PO2-A output*
4
TIOCC3-A output*
5
TIOCC3-A input*
1
*
5
Pin function
IRQ10-B interrupt input*
2
TPU channel 3
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'101
B'101
Output function ⎯ Output
compare
output
⎯ PWM*
3
mode
1 output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCC3-A input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. IRQ10-B input when the ITS10 bit in ITSR is 1.
3. TIOCD3 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_3.
4. When using as PO2-A output, set PPGS in PFCR3 to 0 before other register setting.
5. When using as TIOCC3-A input/output, set TPUS in PFCR3 to 0 before other register
setting.