Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 553 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• Modes 3 and 7 (EXPE = 0)
WAITE ⎯
TPU channel 4
settings
(1) in table below (2) in table below
P25DDR ⎯ 0 0 1
NDER5 ⎯ ⎯ ⎯ 0
P25 input P25 output PO5-A output*
3
TIOCB4-A output*
4
TIOCB4-A input*
1
*
4
Pin function
IRQ13-B interrupt input*
2
Notes: 1. TIOCB4-A input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. IRQ13-B input when the ITS13 bit in ITSR is 1.
3. When using as PO5-A output, set PPGS in PFCR3 to 0 before other register setting.
4. When using as TIOCB4-A input/output, set TPUS in PFCR3 to 0 before other register
setting.
5. WAIT-B input when the WAITS bit in PFCR4 is 1. Not used as WAIT-B input when
WAITS is 0.
TPU channel 4
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'10
B'10
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯
[Legend]
x: Don't care