Datasheet

Section 10 I/O Ports
Page 542 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
SSU
settings
(1) (2) (1) (2) (1) (3) (3) (2) (3) (2) (3) (1) (3) (3) (1) (3) (3)
SSUMS 0 0 1*
1
BIDE 0 1*
2
0
MSS 0 1 0 1 0 1
TE 0 1 0 1 0 1 0 1 0 1 0 1
RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1
Pin state ⎯ SSO
input
⎯ SSO
input
⎯ SSO
output
SSO
output
SSO
input
SSO
output
SSO
input
SSO
output
⎯ SSO
output
SSO
output
⎯ SSO
output
SSO
output
[Legend]
⎯: Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 19.4 to 19.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
• P13/TEND1/PO11/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of bit TEE1 in
DMATCR of the DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits
IOD3 to IOD0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in
TCR_0 to TCR_2, bit NDER11 in NDERH of the PPG, and bit P13DDR.
TEE1 0 1
TPU channel 0
settings
(1) in table
below
(2) in table below ⎯
P13DDR ⎯ 0 1 1 ⎯
NDER11 ⎯ ⎯ 0 1 ⎯
P13 input P13 output PO11 output TEND1 output TIOCD0 output
TIOCD0 input*
1
Pin function
TCLKB input*
2
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
2. TCLKB input when the setting for any of TCR_0 to TCR_2 is TPSC2 to TPSC0 = B'101.
TCLKB input when phase counting mode is set for channels 1 and 5.