Datasheet

Section 10 I/O Ports
Page 534 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
TPU channel 0
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'010
B'010
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯
[Legend]
x: Don't care
• P10/PO8/TIOCA0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of the PPG, and bit P10DDR.
TPU channel 0
settings
(1) in table below (2) in table below
P10DDR ⎯ 0 1
NDER8 ⎯ ⎯ 0 1
P10 input P10 output PO8 output Pin function TIOCA0 output
TIOCA0 input*
1