Datasheet

Section 10 I/O Ports
Page 532 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
TPU channel 0
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOD3 to IOD0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'110
B'110
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯
[Legend]
x: Don't care
• P12/PO10/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2
to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of
the PPG, and bit P12DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P12DDR ⎯ 0 1
NDER10 ⎯ ⎯ 0 1
P12 input P12 output PO10 output TIOCC0 output
TIOCC0 input*
1
Pin function
TCLKA input*
2