Datasheet

Section 10 I/O Ports
Page 530 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• P14/PO12/TIOCA1/SSO0-A
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH,
bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in
PFCR5, and bit P14DDR.
SSU settings (1) in table below (2) in table
below
(3) in table
below
TPU channel 1
settings
(1) in table
below
(2) in table below ⎯
P14DDR ⎯ 0 1 1 0*
5
⎯
NDER12 ⎯ ⎯ 0 1 ⎯
P14
input
P14
output
PO12
output
Pin function TIOCA1
output
TIOCA1 input*
1
SSO0-A
input*
3
*
6
SSO0-A
output*
4
*
6
TPU channel 1
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to B'0011,
B'0101 to B'0111
B'xx00 Other than
B'xx00
Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other
than B'01
B'01
Output
function
⎯ Output compare
output
⎯ PWM*
2
mode
1 output
PWM
mode 2
output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.
2. TIOCB1 output disabled.
3. When using as SSO0-A input, set SSO0S1 and SSO0S0 in PFCR5 to B'00 before other
register setting.
4. When using as SSO0-A output, set SSO0S1 and SSO0S0 in PFCR5 to B'00 before
other register setting.
5. P14DDR = 0 when the SSU pin is used as input.
6. Do not set up for SSU unless SSO0S1 and SSO0S0 = B'00 in PFCR5.
Use as I/O port or TPU pin.