Datasheet
Section 10 I/O Ports 
Page 518 of 1384    R01UH0310EJ0500 Rev. 5.00 
 Sep 25, 2012 
H8S/2426, H8S/2426R, H8S/2424 Group
Mode 3, 7 
Port  Description  Mode 1  Mode 2  Mode 4 
EXPE = 1  EXPE = 0 
Schmitt-
triggered 
input Pin*
2
Input Pull-
up MOS 
Capability 
Open Drain 
Output 
Capability 
5-V 
Tolerance*
1
PA7/A23/CS7/ 
IRQ7-A/SSO0-B 
PA7/A23/CS7/IRQ7A/ 
SSO0-B 
PA7/IRQ7-A/
SSO0-B 
IRQ7-A 
PA6/A22/IRQ6-A/ 
SSI0-B 
PA6/A22/IRQ6-A/ 
SSI0-B 
PA6/IRQ6-A/
SSI0-B 
IRQ6-A 
PA5/A21/IRQ5-A/ 
SSCK0-B 
PA5/A21/IRQ5-A/ 
SSCK0-B 
PA5/IRQ5-A/
SSCK0-B 
IRQ5-A 
A20/IRQ4-A 
PA4/A20/IRQ4-A/ 
SCS0-B 
PA4/IRQ4-A/
SCS0-B 
IRQ4-A 
Port A 
General I/O port 
also functioning 
as address 
outputs, SSU 
I/Os, SCI I/Os, 
and bus control 
signal outputs 
A19 
A18 
A17 
A16 
PA3/A19/SCK4-B 
PA2/A18/RxD4-B 
PA1/A17/TxD4-B 
PA0/A16 
PA3/SCK4-B 
PA2/RxD4-B 
PA1/TxD4-B 
PA0 
⎯ 
O 
All output 
pin 
functions 
other than 
address 
outputs and 
CS7 
⎯ 
A15 PB7/A15 
PB7/TIOCB8/
TCLKH 
TIOCB8/ 
TCLKH 
A14 PB6/A14 PB6/TIOCA8 TIOCA8 
A13 PB5/A13 
PB5/TIOCB7/
TCLKG 
TIOCB7/ 
TCLKG 
A12 PB4/A12 PB4/TIOCA7 TIOCA7 
A11 PB3/A11 
PB3/TIOCD6/
TCLKF 
TIOCD6/ 
TCLKF 
A10 PB2/A10 
PB2/TIOCC6/
TCLKE 
TIOCC6/ 
TCLKE 
A9 PB1/A9 PB1/TIOCB6 TIOCB6 
Port B 
General I/O port 
also functioning 
as address 
outputs and TPU 
I/Os 
A8 PB0/A8 PB0/TIOCA6 TIOCA6 
Ο 
All output 
pin 
functions 
other than 
address 
outputs 
⎯ 
Port C 
General I/O port 
also functioning 
as address 
outputs and TPU 
I/Os 
A7 
A6 
A5 
A4 
A3 
A2 
A1 
A0 
PC7/A7 
PC6/A6 
PC5/A5 
PC4/A4 
PC3/A3 
PC2/A2 
PC1/A1 
PC0/A0 
PC7/TIOCB11 
PC6/TIOCA11 
PC5/TIOCB10 
PC4/TIOCA10 
PC3/TIOCD9 
PC2/TIOCC9 
PC1/TIOCB9 
PC0/TIOCA9 
TIOCB11 
TIOCA11 
TIOCB10 
TIOCA10 
TIOCD9 
TIOCC9 
TIOCB9 
TIOCA9 
Ο 
All output 
pin 
functions 
other than 
address 
outputs 
⎯ 
Port D 
General I/O port 
also functioning 
as data I/Os and 
address outputs 
D15/AD15 
D14/AD14 
D13/AD13 
D12/AD12 
D11/AD11 
D10/AD10 
D9/AD9 
D8/AD8 
PD7 
PD6 
PD5 
PD4 
PD3 
PD2 
PD1 
PD0 
⎯  Ο 
All output 
pin 
functions 
other than 
data 
outputs and 
address 
outputs 
⎯ 










