Datasheet

Section 9 Data Transfer Controller (DTC)
R01UH0310EJ0500 Rev. 5.00 Page 499 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
I
+ Σ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.