Datasheet

Section 9 Data Transfer Controller (DTC)
Page 498 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
9.5.7 Number of DTC Execution States
Table 9.7 lists execution status for a single DTC data transfer, and table 9.8 shows the number of
states required for each execution status.
Table 9.7 DTC Execution Status
Mode
Vector Read
I
Register Information
Read/Write
J
Data Read
K
Data Write
L
Internal
Operations
M
Normal 1 6 1 1 3
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Table 9.8 Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM
On-
Chip
ROM
On-Chip I/O
Registers External Devices
Bus width 32 16 8 16 8 16
Access states 1 1 2 2 2 3 2 3
Vector read S
I
⎯ 1 ⎯ ⎯ 4 6+2m 2 3+m
Register information
read/write S
J
1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Byte data read S
K
1 1 2 2 2 3+m 2 3+m
Word data read S
K
1 1 4 2 4 6+2m 2 3+m
Byte data write S
L
1 1 2 2 2 3+m 2 3+m
Word data write S
L
1 1 4 2 4 6+2m 2 3+m
Execution
status
Internal operation S
M
1