Datasheet

Section 9 Data Transfer Controller (DTC)
R01UH0310EJ0500 Rev. 5.00 Page 491 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Table 9.3 Chain Transfer Conditions
1st Transfer 2nd Transfer
CHNE CHNS DISEL CR CHNE CHNS DISEL CR DTC Transfer
0 ⎯ 0 Not 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer
0 ⎯ 0 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer
0 ⎯ 1 ⎯ ⎯ ⎯ ⎯ ⎯ Interrupt request to CPU
1 0 ⎯ ⎯ 0 ⎯ 0 Not 0 Ends at 2nd transfer
0 ⎯ 0 0 Ends at 2nd transfer
0 ⎯ 1 ⎯ Interrupt request to CPU
1 1 0 Not 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer
1 1 ⎯ 0 0 ⎯ 0 Not 0 Ends at 2nd transfer
0 ⎯ 0 0 Ends at 2nd transfer
0 ⎯ 1 ⎯ Interrupt request to CPU
1 1 1 Not 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer
Interrupt request to CPU