Datasheet

Section 9 Data Transfer Controller (DTC)
R01UH0310EJ0500 Rev. 5.00 Page 489 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
9.5 Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the on-
chip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Figure 9.5 shows a flowchart of DTC operation, and table 9.3 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).