Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 473 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(4) Activation Source Acceptance
At the start of activation source acceptance, low level sensing is used for both falling edge sensing
and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low
level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transfer-
enabled state.
When the EXDMAC is activated, make sure, if necessary, that a low level does not remain at the
EDREQ pin from the previous end of transfer, etc.
(5) Enabling Interrupt Requests when IRF = 1 in EDMDR
When transfer is started while the IRF bit is set to 1 in EDMDR, if the EDIE bit is set to 1 in
EDMDR together with the EDA bit in EDMDR, enabling interrupt requests, an interrupt will be
requested since EDIE = 1 and IRF = 1. To prevent the occurrence of an erroneous interrupt request
when transfer starts, ensure that the IRF bit is cleared to 0 before the EDIE bit is set to 1.
(6) ETEND Pin and CBR Refresh Cycle*
If the last EXDMAC transfer cycle and a CBR refresh cycle* occur simultaneously, note that
although the CBR refresh* and the last transfer cycle may be executed consecutively, ETEND
may also go low in this case for the refresh cycle*.
Note: * Not supported in the 5-V version.