Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 468 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
8.4.12 Ending DMA Transfer
The operation for ending DMA transfer depends on the transfer end conditions. When DMA
transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has
ended.
(1) Transfer End by 1 → 0 Transition of EDTCR
When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel
and the EDA bit in EDMDR is cleared to 0. If the TCEIE bit in EDMDR is set at this time, a
transfer end interrupt request is generated by the transfer counter and the IRF bit in EDMDR is set
to 1.
In block transfer mode, DMA transfer ends when the value of bits 15 to 0 in EDTCR changes
from 1 to 0.
DMA transfer does not end if the EDTCR value has been 0 since before the start of transfer.
(2) Transfer End by Repeat Area Overflow Interrupt
If an address overflows the repeat area when a repeat area specification has been made and repeat
interrupts have been enabled (with the SARIE or DARIE bit in EDACR), a repeat area overflow
interrupt is requested. DMA transfer ends, the EDA bit in EDMDR is cleared to 0, and the IRF bit
in EDMDR is set to 1.
In dual address mode, if a repeat area overflow interrupt is requested during a read cycle, the
following write cycle processing is still executed.
In block transfer mode, if a repeat area overflow interrupt is requested during transfer of a block,
transfer continues to the end of the block. Transfer end by means of a repeat area overflow
interrupt occurs between block-size transfers.
(3) Transfer End by 0-Write to EDA Bit in EDMDR
When 0 is written to the EDA bit in EDMDR by the CPU, etc., transfer ends after completion of
the DMA cycle in which transfer is in progress or a transfer request was accepted.
In block transfer mode, DMA transfer halts after completion of one-block-size transfer.
The EDA bit in EDMDR is not cleared to 0 until all transfer processing has ended. Up to that
point, the value of the EDA bit will be read as 1.