Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 455 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
φ pin
EDACK
Bus cycle
CPU
operation
ETEND
CPU cycle
EXDMA single
transfer cycle
External
space
CPU cycle CPU cycle CPU cycle
1 bus cycle Last transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
External spaceExternal spaceExternal space
Figure 8.29 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(CPU Cycles/Single Address Mode)
φ pin
Bus cycle
Current
channel
EDACK
Other
channel
transfer
request
(EDREQ)
EXDMA
single cycle
1 cycle 1 cycle
1 cycle
Higher-priority channel EXDMA cycle
EXDMA
single cycle
EXDMA
single cycle
EXDMA
single cycle
Bus
release
Bus
release
Bus
release
Bus
release
Bus
release
Figure 8.30 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(Contention with Another Channel/Single Address Mode)