Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 454 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
8.4.11 Examples of Operation Timing in Each Mode
(1) Auto Request/Cycle Steal Mode/Normal Transfer Mode
When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three
cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit
EXDMA cycle and the start of the next transfer.
If there is a transfer request for another channel of higher priority, the transfer request by the
original channel is held pending, and transfer is performed on the higher-priority channel from the
next transfer. Transfer on the original channel is resumed on completion of the higher-priority
channel transfer.
Figures 8.28 to 8.30 show operation timing examples for various conditions.
φ pin
ETEND
Bus cycle
CPU
operation
EDA bit
EXDMA
read
EDA = 1
write
0
0
1
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
3 cycles
1 cycle
Last transfer cycle
Internal bus space
cycles
Bus release
Bus
release
Bus
release
Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode
(No Contention/Dual Address Mode)