Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 450 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
EXDMA read
RD
ETEND
Address bus
φ
Bus release Bus release Bus
release
Last transfer cycle
EDACK
Bus release
EXDMA readEXDMA read
Figure 8.23 Example of Single Address Mode (Word Read) Transfer
After one byte or word has been transferred in response to one transfer request, the bus is released.
While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated.
(2) Single Address Mode (Write)
Figure 8.24 shows an example of transfer when ETEND output is enabled, and byte-size, single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
HWR
ETEND
Address bus
φ
Bus release Bus release Bus release
Last
transfer
cycle
EXDMA
write
EDACK
EXDMA
write
EXDMA
write
EXDMA
write
Bus releaseBus release
LWR
Figure 8.24 Example of Single Address Mode (Byte Write) Transfer