Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 449 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
8.4.10 EXDMAC Bus Cycles (Single Address Mode)
(1) Single Address Mode (Read)
Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.
RD
ETEND
Address bus
φ
Bus release Bus release Bus release
Last
transfer
cycle
EXDMA
read
EDACK
EXDMA
read
EXDMA
read
EXDMA
read
Bus releaseBus release
Figure 8.22 Example of Single Address Mode (Byte Read) Transfer
Figure 8.23 shows an example of transfer when ETEND output is enabled, and word-size, single
address mode transfer (read) is performed from external 8-bit, 2-state access space to an external
device.