Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 447 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(5) EDREQ Pin Low Level Activation Timing
Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level.
EXDMA
read
EXDMA
write
Address bus
φ
EDREQ
Idle Write Idle
Bus release
EXDMA control
Channel
Write Idle
Transfer source
Bus release
EXDMA
read
EXDMA
write
Request
Read Read
Transfer
destination
Transfer source
Transfer
destination
Bus release
[1] [3][2]
[4] [6][5] [7]
Acceptance
resumed
Acceptance
resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle is started.
[4], [7] Acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Minimum 3 cycles
Request
Minimum 3 cycles
Request clearance period Request clearance period
Figure 8.20 Example of Normal Mode Transfer Activated by EDREQ Pin Low Level
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the write cycle, acceptance resumes and EDREQ pin low level
sampling is performed again; this sequence of operations is repeated until the end of the transfer.
Figure 8.21 shows an example of block transfer mode transfer activated by the EDREQ pin low
level.