Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 443 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(2) Normal Transfer Mode (Burst Mode)
Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16-
bit, 2-state access space.
In burst mode, one-byte or one-word transfers are executed continuously until transfer ends.
Once burst transfer starts, requests from other channels, even of higher priority, are held pending
until transfer ends.
EXDMA
read
RD
HWR
ETEND
LWR
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Address bus
φ
Bus
release
Bus
release
Last transfer cycle
Burst transfer
Figure 8.16 Example of Normal Transfer Mode (Burst Mode) Transfer
If an NMI interrupt is generated while a channel designated for burst transfer is enabled for
transfer, the EDA bit is cleared and transfer is disabled. If a block transfer has already been
initiated within the EXDMAC, the bus is released on completion of the currently executing byte or
word transfer, and burst transfer is aborted. If the last transfer cycle in burst transfer has been
initiated within the EXDMAC, transfer is executed to the end even if the EDA bit is cleared.