Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 442 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
8.4.9 EXDMAC Bus Cycles (Dual Address Mode)
(1) Normal Transfer Mode (Cycle Steal Mode)
Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal
transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
After one byte or word has been transferred, the bus is released. While the bus is released, one
CPU, DMAC, or DTC bus cycle is initiated.
EXDMA
read
RD
HWR
ETEND
LWR
EXDMA
write
EXDMA
read
EXDMA
write
EXDMA
read
EXDMA
write
Address bus
φ
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 8.15 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer