Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 431 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(2) Block Transfer Mode
In block transfer mode, the number of bytes or words specified by the block size is transferred in
response to one transfer request. The upper 8 bits of EDTCR specify the block size, and the lower
16 bits function as a 16-bit transfer counter. A block size of 1 to 256 can be specified. During
transfer of a block, transfer requests for other higher-priority channels are held pending. When
transfer of one block is completed, the bus is released in the next cycle.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during block transfer.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block
ends. The EDRAK signal is output once for one transfer request (for transfer of one block).
Caution is required when setting the repeat area overflow interrupt of the repeat area function in
block transfer mode. See section 8.4.6, Repeat Area Function, for details.
Block transfer is aborted if an NMI interrupt is generated. See section 8.4.12, Ending DMA
Transfer, for details.
Figure 8.8 shows an example of DMA transfer timing in block transfer mode.
CPUCPU CPU EXDMAC EXDMAC EXDMAC CPU
Bus cycle
EDRAK
ETEND
EDREQ
CPU cycle not generated
One-block transfer cycle
Transfer conditions:
· Single address mode
· BGUP = 0
· Block size (EDTCR[23:16]) = 3
Figure 8.8 Example of Timing in Block Transfer Mode