Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 429 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(2) Burst Mode
In burst mode, once the EXDMAC acquires the bus it continues transferring data, without
releasing the bus, until the transfer end condition is satisfied. There is no burst mode in external
request mode.
In burst mode, once transfer is started it is not interrupted even if there is a transfer request from
another channel with higher priority. When the burst mode channel finishes its transfer, it releases
the bus in the next cycle in the same way as in cycle steal mode.
When the EDA bit is cleared to 0 in EDMDR, DMA transfer is halted. However, DMA transfer is
executed for all transfer requests generated within the EXDMAC up until the EDA bit was cleared
to 0.
If a repeat area overflow interrupt is generated, the EDA bit is cleared to 0 and transfer is
terminated.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during burst transfer. If there is no bus request, burst transfer is executed even if the
BGUP bit is set to 1.
Figure 8.6 shows examples of the timing in burst mode.
CPU CPU CPU CPU
Bus cycle
EXDMAC operates alternately with CPU
EXDMAC EXDMAC EXDMAC
Transfer conditions:
Auto request mode, BGUP = 1
CPU
CPU CPU CPU
Bus cycle
CPU cycle not generated
EXDMAC EXDMAC EXDMAC
Transfer conditions:
Auto request mode, BGUP = 0
Figure 8.6 Examples of Timing in Burst Mode