Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 428 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
8.4.4 Bus Modes
There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto
request, either cycle steal mode or burst mode can be selected. When the activation source is an
external request, cycle steal mode is used.
(1) Cycle Steal Mode
In cycle steal mode, the EXDMAC releases the bus at the end of each transfer of a transfer unit
(byte, word, or block). If there is a subsequent transfer request, the EXDMAC takes back the bus,
performs another transfer-unit transfer, and then releases the bus again. This procedure is repeated
until the transfer end condition is satisfied.
If a transfer request occurs in another channel during DMA transfer, the bus is temporarily
released, then transfer is performed on the channel for which the transfer request was issued. If
there is no external space bus request from another bus master, a one-cycle bus release interval is
inserted. For details on the operation when there are requests for a number of channels, see section
8.4.8, Channel Priority Order.
Figure 8.5 shows an example of the timing in cycle steal mode.
CPU CPU CPU CPUEXDMAC EXDMAC
Bus returned temporarily to CPU
EDREQ
EDRAK
Bus cycle
Transfer conditions:
· Single address mode, normal transfer mode
· EDREQ low level sensing
· CPU internal bus master is operating in external space
Figure 8.5 Example of Timing in Cycle Steal Mode