Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 416 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
6 IRF 0 R/(W)* Interrupt Request Flag
Flag indicating that an interrupt request has
occurred and transfer has ended.
0: No interrupt request
[Clearing conditions]
• Writing 1 to the EDA bit
• Writing 0 to IRF after reading IRF = 1
1: Interrupt request occurrence
[Setting conditions]
• Transfer end interrupt request generated by
transfer counter
• Source address repeat area overflow interrupt
request
• Destination address repeat area overflow
interrupt request
5 TCEIE 0 R/W Transfer Counter End Interrupt Enable
Enables or disables transfer end interrupt requests
by the transfer counter. When transfer ends
according to the transfer counter while this bit is set
to 1, the IRF bit is set to 1, indicating that an
interrupt request has occurred.
0: Transfer end interrupt requests by transfer
counter are disabled
1: Transfer end interrupt requests by transfer
counter are enabled
4 SDIR 0 R/W Single Address Direction
Specifies the data transfer direction in single
address mode. In dual address mode, the
specification by this bit is ignored.
0: Transfer direction: EDSAR → external device
with DACK
1: Transfer direction: External device with DACK→
EDDAR