Datasheet

Section 7 DMA Controller (DMAC)
Page 398 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
7.5.15 Forced Termination of DMAC Operation
If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops
on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the
DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL.
Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
Forced termination
of DMAC
Clear DTE bit to 0
Forced termination
[1]
[1] Clear the DTE bit in DMABCRL to 0.
To prevent interrupt generation after forced
termination of DMAC operation, clear the DTIE bit
to 0 at the same time.
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation