Datasheet

Section 7 DMA Controller (DMAC)
Page 396 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles*
1
,
and EXDMAC*
2
When the DMAC accesses external space, contention with a refresh cycle*
1
, EXDMAC cycle*
2
, or
external bus release cycle may arise. In this case, the bus controller will suspend the transfer and
insert a refresh cycle*
1
, EXDMAC cycle*
2
, or external bus release cycle, in accordance with the
external bus priority order, even if the DMAC is executing a burst transfer or block transfer. (An
external access by the DTC or CPU, which has a lower priority than the DMAC, is not executed
until the DMAC releases the external bus.)
When the DMAC transfer mode is dual address mode, the DMAC releases the external bus after
an external write cycle. The external read cycle and external write cycle are inseparable, and so the
bus cannot be released between these two cycles.
When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC
cycle may be executed at the same time as a refresh cycle*
1
, EXDMAC cycle*
2
, or external bus
release cycle.
Notes: 1. Not supported in the 5-V version.
2. Not supported in the H8S/2424 Group.