Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 387 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single
address mode transfer (write) is performed from an external device to external 8-bit, 2-state access
space.
DMA write
Address bus
φ
DMA write DMA write
DMA
dead
HWR
TEND
DACK
Bus
release
LWR
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 7.29 Example of Single Address Mode Transfer (Word Write)
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.