Datasheet

Section 7 DMA Controller (DMAC)
Page 374 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles
(1) Short Address Mode
Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short
address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state
access space to internal I/O space.
DMA
read
Address bus
φ
RD
LWR
TEND
HWR
Bus release Last transfer
cycle
DMA
write
DMA
dead
DMA
read
DMA
write
DMA
read
DMA
write
Bus release Bus release Bus
release
Figure 7.18 Example of Short Address Mode Transfer
A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND output is enabled, TEND output goes low in the transfer end cycle.