Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 369 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area.
Address T
B
Address B
B
Transfer
Address T
A
Address B
A
1st block
2nd block
Nth block
Block area
Consecutive transfer
of M bytes or words
is performed in
response to one
request
[Legend]
Address
Address
Address
Address
Where:
= L
A
= L
B
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N – 1))
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (M·N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
T
A
T
B
B
A
B
B
L
A
L
B
N
M
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1)