Datasheet

Section 7 DMA Controller (DMAC)
Page 364 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 7.11 illustrates operation in normal mode.
Address T
A
Address B
A
Transfer
Address T
B
[Legend]
Address
Address
Address
Address
Where:
Address B
B
= L
A
= L
B
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N – 1))
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (N – 1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRA
T
A
T
B
B
A
B
B
L
A
L
B
N
Figure 7.11 Operation in Normal Mode