Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 361 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 7.9 illustrates operation in single address mode (when sequential mode is specified).
Address T
Address B
Transfer
DAC
K
1 byte or word transfer performed in
response to 1 transfer request
[Legend]
Address T = L
Address B = L + (–1)
DTID
· (2
DTSZ
· (N – 1))
Where: L = Value set in MAR
N = Value set in ETCR
Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified)