Datasheet

Section 7 DMA Controller (DMAC)
Page 358 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 7.7 illustrates operation in repeat mode.
Address T
Address B
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
[Legend]
Address T = L
Address B = L + (–1)
DTID
· (2
DTSZ
· (N – 1))
Where: L = Value set in MAR
N = Value set in ETCR
Figure 7.7 Operation in Repeat mode
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit data empty and receive data full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.