Datasheet

Section 7 DMA Controller (DMAC)
Page 356 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
7.5.4 Repeat Mode
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in
DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to
a single transfer request, and this is executed the number of times specified in ETCRL. On
completion of the specified number of transfers, MAR and ETCRL are automatically restored to
their original settings and operation continues. One address is specified by MAR, and the other by
IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7
summarizes register functions in repeat mode.
Table 7.7 Register Functions in Repeat Mode
Function
Register DTDIR = 0 DTDIR = 1 Initial Setting Operation
23 0
MAR
Source
address
register
Destination
address
register
Start address of
transfer destination
or transfer source
Incremented/
decremented every
transfer.
Initial setting is
restored when the
value reaches
H'0000
23 15 0
IOARH'FF
Destination
address
register
Source
address
register
Start address of
transfer source or
transfer destination
Fixed
0
ETCRAH
7
Holds number of
transfers
Number of transfers Fixed
0
ETCRAL
7
Transfer counter Number of transfers Decremented every
transfer.
Loaded with ETCRH
value when the
value reaches H'00