Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 353 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
7.5.3 Idle Mode
Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In
idle mode, one byte or word is transferred in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6
summarizes register functions in idle mode.
Table 7.6 Register Functions in Idle Mode
Function
Register DTDIR = 0 DTDIR = 1 Initial Setting Operation
23 0
MAR
Source
address
register
Destination
address
register
Start address of
transfer destination
or transfer source
Fixed
23 15 0
IOARH'FF
Destination
address
register
Source
address
register
Start address of
transfer source or
transfer destination
Fixed
015
ETCR
Transfer counter Number of transfers Decremented every
transfer; transfer
ends when count
reaches H'0000
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address. The upper 8 bits of IOAR have a value of H'FF.