Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 341 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. If the DTE1 bit is cleared
to 1 when DTIE1A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE1A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE1 bit to 1.
1 DTIE0B 0 R/W Data Transfer Interrupt Enable 0B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted. If
the DTME0 bit is cleared to 0 when DTIE0B = 1,
the DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either
by clearing the DTIE0B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME0 bit to 1.
0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A
Enables or disables an interrupt to the CPU or
DTC when transfer ends. If the DTE0 bit is cleared
to 0 when DTIE0A = 1, the DMAC regards this as
indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE0A bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE0 bit to 1.