Datasheet

Section 7 DMA Controller (DMAC)
Page 338 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
6 DTE1 0 R/W Data Transfer Enable 1
Enables or disables DMA transfer for the
activation source selected by the DTF3 to DTF0
bits in DMACR of channel 1.
When DTE1 = 0, data transfer is disabled and the
activation source is ignored. If the activation
source is an internal interrupt, an interrupt request
is issued to the CPU or DTC. If the DTE1 bit is
cleared to 0 when DTIE1 = 1, the DMAC regards
this as indicating the end of a transfer, and issues
a transfer end interrupt request to the CPU.
When DTE1 = 1 and DTME1 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
• When initialization is performed
• When the specified number of transfers have
been completed
• When 0 is written to the DTE1 bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE1 bit after reading
DTE1 = 0