Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 337 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• DMABCRL
Bit Bit Name Initial Value R/W Description
7 DTME1 0 R/W Data Transfer Master Enable 1
Together with the DTE1 bit, this bit controls
enabling or disabling of data transfer on channel
1. When both the DTME1 bit and DTE1 bit are set
to 1, transfer is enabled for channel 1.
If channel 1 is in the middle of a burst mode
transfer when an NMI interrupt is generated, the
DTME1 bit is cleared, the transfer is interrupted,
and bus mastership passes to the CPU. When the
DTME1 bit is subsequently set to 1 again, the
interrupted transfer is resumed. In block transfer
mode, however, the DTME1 bit is not cleared by
an NMI interrupt, and transfer is not interrupted.
[Clearing conditions]
• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME1 bit
[Setting condition]
When 1 is written to DTME1 after reading
DTME1 = 0